FIGURE 11.70
• DIGITAL VLSI CHIP- 32 PROCESSORS IN PARALLEL
• A PROCESSOR IS BASICALLY A HARDWARE MULTIPLY-AND-ACCUMULATE (MAC) UNIT (1.33 ns WITH 25-MHz CLOCK)
• CONFIGURABLE INTO SINGLE-LAYER OR MULTILAYER MLP (MULTILAYER PERCEPTRON) TYPE NETWORK
• 16-BIT DATA RESOLUTION
• 8-BIT WEIGHT RESOLUTION
• 64-KBIT DYNAMIC RAM STORAGE OF WEIGHTS
• FOUR (EXTERNAL) 16-BIT SRAM LOOK-UP TABLE
• ACTIVATION FUNCTIONS
• REACTIVE TABU SEARCH (RTS) TRAINING ALGORITHM
• 5-jis FEEDFORWARD COMPUTATION TIME
• MULTIPLE NC3003 CHIPS (UP TO FOUR) CAN BE CONNECTED
IN PARALLEL WITH PROPORTIONATELY HIGHER COMPUTATION TIME
• CHIPS OPERATE IN HOST PROCESSOR ENVIRONMENT
The salient features of the Neuricam NC3003 IC chip discussed in the preceding figure are summarized here. Note that internally the chip consists of software programmable multiple DSPs, where the speed is enhanced by its pipelined architecture. Although individual MAC instruction takes only 1.33 ns, a typical two-unit NC3003 system takes about 10 |js for feedforward computation. This is far slower than the usually expected parallel processing ASIC chip. The training of the chip requires the usual input-output data table, but a special RTS algorithm is used. The advantage compared to the back-propagation algorithm is that it does not require derivatives of error signals, thus avoiding the need for high-precision computation. The fixed-point short-word digital implementation made possible by RTS leads to more economical VLSI architectures than its floating-point, long-word format counterparts, thus saving silicon estate, power dissipation, and speed. It appears that in spite of worldwide intensive research, the ultimate fully functional custom digital ASIC chip for NNW implementation is a far cry from being realized [27].
Introduction To Power Electronics And Motor Drives
