• 16-BIT FIXED POINT
• COMPUTATION RATE: 33 MIPS (30-ns CYCLE TIME)
• 9K WORDS PROGRAM/DATA RAM (SINGLE-CYCLE)
• 1K WORD DATA RAM (DUAL-ACCESS)
• 2K WORDS BOOT ROM
• ONE 16-BIT TIMER
• TWO SERIAL PORTS (ONE FULL DUPLEX)
• 192K WORDS ADDRESSABLE MEMORY
• 16 x 16 -BIT MULTIPLIER (32-BIT PRODUCT)
• 64K x 16 PARALLEL PORTS
• SOURCE CODE COMPATIBLE WITH C1X/C2X FAMILIES
• 16-BIT PARALLEL LOGIC UNIT (PLU)
• 16 S/W PROGRAMMABLE WAIT STATE GENERATORS
• ASSEMBLY AND C LANGUAGE SUPPORT
• FULLY STATIC 0.72-^M CMOS FOR LOW POWER CONSUMPTION
The TI C50 DSP is a 16-bit fixed-point device that is suitable for use in most power electronic systems. However, the data step size is larger (as inherent in a fixed-point DSP), and, therefore, its dynamic range is smaller compared to similar floating-point DSPs. Therefore, to prevent data overflow/underflow, suitable scaling may be needed. One special feature of the device is that it uses a fully static CMOS device that contributes to low power consumption and, therefore, a battery power supply can be used. The high speed of computation is due to its Harvard architecture (in which two separate bus sets are used to transport instructions and date independently). The addition of a PLU provides the power to manipulate bits in data memory without using accumulator and ALU. The programmable wait states permit the DSP to interface with slower devices. The DSP supports a large number of parallel ports which may be convenient in some applications.