FIGURE 9.26
• COMPUTATION RATE: 33 MFLOPS (60-ns CYCLE TIME)
• 2K 32-BIT RAM
• 4K 32-BIT ROM
• 64 x 32-BIT CACHE MEMORY
• 32-BIT INSTRUCTION AND DATA WORDS, 24-BIT ADDRESSES
• 40/32-BIT FLOATING-POINT/INTEGER MULTIPLIER
• 32-BIT BARREL SHIFTER
• TWO 32-BIT TIMERS
• DIRECT MEMORY ACCESS (DMA) CAPABILITY
• INTEGER, FLOATING-POINT, AND LOGICAL OPERATIONS
• TWO BIDIRECTIONAL SERIAL PORTS
• FOUR EXTERNAL INTERRUPTS
• ASSEMBLY AND C-LANGUAGE SUPPORT
• 1.0-mM CMOS VLSI CHIP, + 5-VSUPPLY
The TI C30 DSP has been widely used in power electronic systems. One advantage of large word-size (32-bit) floating-point computation is that the signal step is very small, i.e., the resolution is high, and the large dynamic range does not require any scaling to prevent signal overflow or underflow. Of course, the DSP permits data conversion between the floating-point and integer formats and computation in either format. The computation speed is very fast as indicated. Each RAM and ROM block is capable of supporting two CPU accesses in a single cycle. The cache memory permits fast access of the often-repeated part of the program. The barrel shifter is used to shift up to 32 bits left or right in a single cycle. The DMA access permits fast data input/output operation without interfering with CPU operation. Both the hardware counters are of the incrementing type and can be programmed in various ways. Two serial ports are independent, and can be programmed as transmitter or receiver supporting 8/16/24/32-bit data transfers. Off-chip memory and I/O devices can be accessed by compatible access time devices. The slower devices need WAIT states for data transfer.